/**
 * @file ictl.h
 * @brief T1 Interrupt Controller
 *
 * @author yemt@witsi.cn
 * @date 2011-08-04
 * @version T1.ICTL.01
 */
#ifndef T1_ICTL_H_
#define T1_ICTL_H_

#include "iodef.h"

typedef struct {
        __IO uint32_t INT_EN;           /**< Interrupt Source Enable Register */
        __IO uint32_t Reserved1;
        __IO uint32_t INT_MASK;         /**< Interrupt Source Mask Register */
        __IO uint32_t Reserved2;
        __IO uint32_t INT_FORCE;        /**< Interrupt Force Register */
        __IO uint32_t Reserved3;
        __IO uint32_t INT_RS;           /**< Interrupt Raw Status Register */
        __IO uint32_t Reserved4;
        __IO uint32_t INT_STA;          /**< Interrupt Status Register */
        __IO uint32_t Reserved5;
        __IO uint32_t INT_MS;           /**< Interrupt Mask Status Register */
        __IO uint32_t Reserved6;
        __IO uint32_t INT_FS;           /**< Interrupt Final Status Register */
}ictl_reg_t;

typedef enum
{
        IRQ_CP0_COUNT = -1,             /**< CP0 Counter Interrupt */
        IRQ_UART0 = 0,                  /**< UART 0 Interrupt */
        IRQ_UART1,                      /**< UART 1 Interrupt */
        IRQ_UART2,                      /**< UART 2 Interrupt */
        IRQ_UART3,                      /**< UART 3 Interrupt */
        IRQ_WDT,                        /**< Watchdog Timer Interrupt */
        IRQ_GPIO,                       /**< GPIO Interrupt */
        IRQ_TIMER,                      /**< Timers Interrupt */
        IRQ_DAC,                        /**< DAC Interrupt */
        IRQ_SPI0,                       /**< SPI0 Interrupt */
        IRQ_SPI1,                       /**< SPI1 Interrupt */
        IRQ_Reserved1,
        IRQ_SYSTEM,                     /**< System Configuration Interrupt */
        IRQ_CRYPTO,                     /**< Cryptography Interrupt */
        IRQ_Reserved2,
        IRQ_MAGCARD,                    /**< Magnetic Card Reader Interrupt */
        IRQ_USB,						/**< Usb Interrupt */
        IRQ_ISO0_IO0,                   /**< ISO0 IO0 Interrupt */
        IRQ_ISO0_IO1,                   /**< ISO0 IO1 Interrupt */
        IRQ_ISO0_IO2,                   /**< ISO0 IO2 Interrupt */
        IRQ_ISO0_RST,                   /**< ISO0 RST Interrupt */
        IRQ_ISO1_IO0,                   /**< ISO1 IO0 Interrupt */
        IRQ_ISO1_IO1,                   /**< ISO1 IO1 Interrupt */
        IRQ_ISO1_IO2,                   /**< ISO1 IO2 Interrupt */
        IRQ_ISO1_RST,                   /**< ISO1 RST Interrupt */
        IRQ_ISO2_IO0,                   /**< ISO2 IO0 Interrupt */
        IRQ_ISO2_IO1,                   /**< ISO2 IO1 Interrupt */
        IRQ_ISO2_IO2,                   /**< ISO2 IO2 Interrupt */
        IRQ_ISO2_RST,                   /**< ISO2 RST Interrupt */
        IRQ_DEFENDER,					/**< Defender Interrupt */
        IRQ_RTC,
        IRQ_FSK,
        IRQ_MAX
}int_type_t;

#define ICTL    ((ictl_reg_t *)T1_ICTL_BASE)    /**< Interrupt Controller Register Address */

#endif /* T1_ICTL_H_ */
